Senior Engineer – ASIC/ SoC Physical Design

Job Description: • Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation • Block level implementation from netlist to GDS • Handling timing closure of high frequency blocks • Handling blocks of high instance counts – 1M instance and above • Expertise in signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level • Understanding constraints and fixing techniques • Understanding SI prevention, fixing methodology and implementation • Proficient in layout edit techniques • Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set • Experience in Design Automation and UNIX system • Experience in Tcl/Tk, PERL is a plus Desired Skills & Experience: • Required experience level is 3 to 6 years • Must possess required hands on experience in handling block/chip level implementation from Netlist to GDS • Must possess hands on experience in timing closure and physical verification closure • Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz • Experience in handling lower tech nodes that include 14nm, 28nm, 40nm using tools ICC or SOC Encounter • Ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time • Experience in Synthesis and Formal is a plus • Excellent verbal and written communication skills along with debug skills, analytical skills and the ability to work independently Education: UG - B.Tech/B.E. Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, Electrical, Electronics/Telecommunication)

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