Intern on VLSI/ASIC design verification

SmartchipDesign Profile:

Smart chip design is a premier institute for higher learning in VLSI / ASIC design and verification. The training programs cover the advanced latest tools and technologies in VLSI training.

Smart chip design a revered institute of in the field of VLSI/ASIC training aim to provide world-class education with optimum level of research, creativity and service for this sector. VLSI/ASIC Design and verification is extremely challenging role, which will be developing the next generation Intellectual property.

Descriptions:

1. The selected intern candidate will be part of the IP verification/ VIP team in Group, smartchipdesign , India and be based at Bangalore.

2. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ UVM environment in one of the following domain SPI,Ethernet,UART,AHB,APB,USB,AXI

3. The training will be taken through hands-on training in Verification methodologies such as UVM and in the respective domain.

4. Subsequent to training, the nature of work would be on the following lines:

5. Understanding IP/SoC architecture for VIP or Test environment, coding in one of the HVL such as System Verilog,UVM Verification of the blocks that are coded, understanding and implementing functional coverage infrastructure. It will involve closely working as part of the IP/SoC development team.

Candidate Profile:

1. The candidate must have BE/BTech, ME/MTech,MSc(electronics) in electronics/ Electrical engg with minimum 60% or 6.0 CGPA.

2. Partial or full completion of BE/BTech, ME/MTech,MSc(electronics) in electronics/ Electrical is preferable with overall grades of 6.0 or above.

(Please mention NCRJobs.in for reference)

(Please mention NCRJobs.in for reference)

Location :

Address :