VLSI trainee

VLSI trainee

VLSI trainee

  • Posted 3681 day(s) ago
  • Job Views : 234
  • Job Applicants : 0

Job Description

Eligibility BE/BTech, ME/MTech,MSc(electronics) Experience Freshers Location Bengalore Job Role Intern on ASIC Design & Verification (VLSI) JOB SUMMARY: Company Profile: Smart chip design is a premier institute for higher learning in VLSI / ASIC design and verification. The training programs cover the advanced latest tools and technologies in VLSI training. Smart chip design a revered institute of in the field of VLSI/ASIC training aim to provide world-class education with optimum level of research, creativity and service for this sector. VLSI/ASIC Design and verification is extremely challenging role, which will be developing the next generation Intellectual property. smartchipdesign comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. Job Descriptions: 1. The selected intern candidate will be part of the IP verification/ VIP team in Solutions Group, smartchipdesign , India and be based at Bangalore. 2. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ UVM environment in one of the following domain :USB3/USB2/Ethernet/MIPI 3. The intern will be taken through hands-on training in Verification methodologies such as UVM and in the respective domain. 4. Subsequent to training, the nature of work would be on the following lines: 5. Understanding product architecture for VIP or Test environment, coding in one of the HVL such as System Verilog,UVM Verification of the blocks that are coded, understanding and implementing functional coverage infrastructure. It will involve closely working as part of the product development team. Candidate Profile: 1. The candidate must have BE/BTech, ME/MTech,MSc(electronics) in electronics/ Electrical engg with minimum 70% or 7.0 CGPA. 2. Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above.

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Short Description
  • Job ID:

    NCRJB3015
  • Job Views:

    234
  • Job Type:

    full time
  • Number of Vacancies:

    0
  • Industry:

  • Functional Area:

  • Job Experience:

  • Posted On:

    07, Sep 2014
  • Closing Date:

    01, Jan 1970